Memory Layout Design Engineer

VMware · Cloud, Infra & DevTools · IND-Bangalore Electronic City - S1

IND-Bangalore Electronic City - S1Ingeniería3 de agosto de 2026Leído en Workday
Presencial

Vigencia de la oferta

Más de un mesVerificada en el sitio del editor hace 2 h

Activa desde hace más de un mes. El puesto probablemente sigue abierto, pero el reclutador ya ha recibido candidaturas.

  • Activa desde hace 43 d
  • VMware retira sus ofertas al cabo de 16 d de mediana (22 ofertas cerradas observadas)

Comprobado cada seis horas en el sitio del editor. La antigüedad cuenta desde la fecha de publicación original, incluso tras una republicación.

Descripción

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Job Description:

Job Requirements:

  • Minimum 8+ years of experience with a Bachelor's degree or 6+ years of experience with a Master's degree, strong layout knowledge.
  • Proficiency in using Cadence tools (Virtuoso Layout, Layout XL, Cadence Schematic Capture, and verification tools - Calibre & Hercules).
  • Strong layout knowledge in advanced submicron FinFET processes, including  TSMC 5nm, 3nm, 2nm, A14 or Samsung lower FinFET nodes.


Key Responsibilities:

  • Understand and apply layout guidelines, new process rules, and technical requirements for high-quality layouts.
  • Manage scheduling, timelines, and layout floor-planning.
  • Ensure end-to-end deliverables are completed with high quality and within the planned schedule.
  • Adapt quickly to new methodologies and communicate effectively with the SOC and library teams.


Skill Set(Memory):

  • Proven ability to manage schedules, timelines, and end-to-end deliverables.
  • Experienced in leading teams, training junior engineers, and documenting layout methodologies and guidelines.
  • Proficient in Cadence tools, including Virtuoso Layout, Layout XL, VXL, EXL, and Cadence Schematic Capture.
  • Strong experience in memory layout design and physical verification (LVS, DRC, ERC, Antenna, Electro Migration) in CMOS processes.
  • Extensive experience with physical verification tools such as Calibre and Hercules (DRC, LVS, ERC, Antenna, and Softcheck Errors).
  • Proficiency in floor-planning, hierarchy layout, and chip integration.
  • Solid understanding of memory architecture and RC requirements, with the ability to plan signal and power routing.
  • Ability to lead teams, train junior engineers, and manage projects effectively.
  • Strong knowledge of memory layout topology; experience with memory compilers is preferred.
  • Knowledge of AI, layout automation, and script/SKILL programming is preferred.
  • Ability to lead new technology reviews to document layout methodologies, flows, and guidelines.
  • Self-reliant with the ability to work both independently and collaboratively.

Broadcom is proud to be an equal opportunity employer.  We will consider qualified applicants without regard to race, color, creed, religion, sex, sexual orientation, national origin, citizenship, disability status, medical condition, pregnancy, protected veteran status or any other characteristic protected by federal, state, or local law.  We will also consider qualified applicants with arrest and conviction records consistent with local law.

If you are located outside USA, please be sure to fill out a home address as this will be used for future correspondence.

En resumen

Publicada el 3 de agosto de 2026 · vista por primera vez el 6 de septiembre de 2026

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