EMIR/ESD Engineer

Cisco · Hardware & Semi-conducteurs · Armenia

ArmeniaInfra & Data14 septembre 2026Lu sur Workday
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Ce que dit l'annonce

Perform chip-level EMIR and ESD analysis for Cisco's ASIC designs, optimize power grid performance, and collaborate on physical implementation from RTL to GDSII.

  • 3+ ans d'expérience
  • Contributeur individuel

Lu dans le texte de l'annonce par un modèle de langage le 14 septembre 2026 — indicatif, vérifiez sur l'annonce d'origine.

Description

Meet the Team


Step into Cisco's ASIC Physical Design Team, where innovation meets collaboration. As a group of highly skilled engineers, we're redefining what's possible in silicon technology. Our mission is to drive the future of chip design, managing full chip physical implementation from RTL to GDSII and beyond. Working hand-in-hand with Front-End teams, we transform cutting-edge designs into industry-leading silicon solutions. Here, you'll have the opportunity to shape tomorrow's technology, driving advancements in power, performance, and reliability with every project. Together, we're building the foundation for the future of connectivity.


Your Impact


Drive Cisco's silicon innovation by performing comprehensive chip-level EMIR and ESD analysis to ensure the reliability of our next-generation designs. Investigate complex EMIR and ESD results to propose and implement effective optimizations that maintain design integrity. Collaborate with package teams and block owners to guide design fixes and ensure robust power grid performance. Coordinate with EDA tool vendors and flow teams to enhance the accuracy and scalability of our sign-off methodologies. Contribute to the end-to-end physical implementation process to ensure our silicon solutions meet the highest standards for performance and reliability before tape-out.


 Minimum Qualifications

  • Bachelor's or Master's degree in Electrical Engineering or Computer Science.
  • Minimum of 3 years of hands-on experience in ASIC design and verification.
  • Strong understanding of schematics and layout in FinFET technologies.
  • Experience in deep submicron CMOS technologies.
  • Hands-on experience in RTL-to-GDSII flow, floorplanning, and power planning.

 Preferred Qualifications

  • Good knowledge of ESD protection concepts and implementation.
  • Familiarity with PnR and verification tools such as Synopsys, Cadence, or Siemens.
  • Strong scripting skills in Python, TCL, or Bash.
  • Ability to collaborate effectively with cross-functional teams and external vendors.
  • Experience in full-chip physical design and tape-out processes.

Why Cisco? 

At Cisco, we’re revolutionizing how data and infrastructure connect and protect organizations in the AI era – and beyond. We’ve been innovating fearlessly for 40 years to create solutions that power how humans and technology work together across the physical and digital worlds. These solutions provide customers with unparalleled security, visibility, and insights across the entire digital footprint.

Fueled by the depth and breadth of our technology, we experiment and create meaningful solutions. Add to that our worldwide network of doers and experts, and you’ll see that the opportunities to grow and build are limitless. We work as a team, collaborating with empathy to make really big things happen on a global scale. Because our solutions are everywhere, our impact is everywhere. 

We are Cisco, and our power starts with you. 

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Publiée le 14 septembre 2026 · vue pour la première fois le 8 septembre 2026

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